The best advice I ever got when I started to play with Verilog and FPGAs in undergrad was that one should think of the circuit first, then write the Verilog to describe it. As another poster said, this isn't programming; there are no usual sequential semantics (first compute this, then assign that value) even though code samples may look that way. The tricky (slash insanely cool) thing about HDLs is that they infer a lot of things -- latches, MUXes, ALUs -- out of a high-level description. But the abstraction is leaky, so you need to understand digital logic (state machines, latches, pipelines, ...) and then work up from there.

I guess what I'm really trying to say is, study digital logic first, then imagine the circuit you want to build, then write the Verilog that infers that circuit :-)