Completely wild to me that you are backing out the netlist from the geometry gds... | Hacker News

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		tmvphil on Jan 8, 2025 \| parent \| context \| favorite \| on: Gate-level simulation of ASIC in browser Completely wild to me that you are backing out the netlist from the geometry gds.

znah on Jan 8, 2025 [–]

First I implemented it, and then learned that it is called Layout vs Schematic (LVS). For now automatic conversion is limited to stateless cells, but I'm planning to rewrite the circuit extractor to support all flipflops and latches.

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