The thing is, with every chip generation the non recurring engineering costs are heavily swinging towards FPGAs staying competitive at ever higher volumes. If you're happy with a CPU+FPGA combo and want to take advantage of 12 nm but your design fits on an FPGA, then it almost never makes sense to design an ASIC.

Your design would in principle have to be an analog design or something that simply cannot take advantage of smaller nodes i.e. MEMS.