I would have believed this before the M1, but now I think fixed-width instructions are great for parallel decode, so there's a real threat now which is attributable to RISC.
Fixed-width decode only one of the ideas of "RISC," but not the main one. I would argue that modern ARM is almost as much of a CISC-y abomination as was x86 in 1999. ARM has a lot of instructions that do multiple things and are very non-RISC.
POWER is probably the most RISC-y architecture in use at the high end right now, but it still looks like CISC to the people who originally came up with that idea.
