AMD didn't have to introduce a special driver for the Ryzen 9 5950x to keep threads resident to the "gaming" CCD. There was only a small difference between the 5950x and the non-X3d Ryzen 7 5800x in workloads that didn't use more than 8 cores unlike the observed slowdowns in the Ryzen 9s 7950X3D and 7900X3D when they were released compared to the Ryzen 7 7800X3D .
When the L3 sizes are different across CCDs the special AMD driver is needed to keep threads pinned to the larger L3 CCD and prevent them from being placed on the small L3 CCD where their memory requests can exploit the other CCD's L3 as an L4. The AMD driver reduces CCD to CCD data requests by keeping programs contained in one CCD.
With equal L3 caches when a process spills onto the second CCD it will still use the first's L3 cache as "L4" but it no longer has to evict that data at the same rate as the lopsided models. Additionally the first CCD can use the second CCD's L3 in kind reducing the number of requests that need to go to main memory.
The same sized L3s reduce contention to the IO die and the larger sized L3s reduce memory contention, it's a win-win.
You could've written that comment in a more constructive way.
As you probably already know, my point was that it's a bit callous to focus on "this war is expensive and inconvenient" while innocent people are, you know, dying.
> Though the other day I learned there are many technologies for "RAM"
I'm an advocate of sticking a $5 16Gb Optane stick from eBay on a $10 M.2 to PCIe 1x adapter from eBay. Set it up as swap in Windows or Linux. Or pay $200 for a 16GB stick of DDR5.
ECC is actually slower. The hardware to compute every transaction is correct does add a slight delay, but nothing compared to the delay of working on corrupted data.
The solar panels on the newest satellites can deliver 6kW but the power that satellite actually uses is less. The satellite is only using 300W[1] during the dark phase of it's orbit when it can use it's entire mass to cool down. Is that limit because of the battery or is it because the satellite needs to radiate all the heat it acquired from the other half of the time in the sun?
Looks like that's a purely speculative assumption the blog author made, not a fact. I'm not sure why he made that assumption given that Starlink doesn't actually stop working at night.
Fair point that in SSO you'd need 2-3x the radiator area (and half the solar panels, and minimal/no batteries). I don't think that invalidates my point though.
If the satellite requires ~3,000 W to work in the light phase (based on solar panel size), then reducing that to 300 W during the dark phase would most definitely require it to "stop working".
The battery math is based on purely speculative assumptions the author made about cycle lifetimes. It's not grounded in any real, concrete information like the solar panel power calculations are.
When the L3 sizes are different across CCDs the special AMD driver is needed to keep threads pinned to the larger L3 CCD and prevent them from being placed on the small L3 CCD where their memory requests can exploit the other CCD's L3 as an L4. The AMD driver reduces CCD to CCD data requests by keeping programs contained in one CCD.
With equal L3 caches when a process spills onto the second CCD it will still use the first's L3 cache as "L4" but it no longer has to evict that data at the same rate as the lopsided models. Additionally the first CCD can use the second CCD's L3 in kind reducing the number of requests that need to go to main memory.
The same sized L3s reduce contention to the IO die and the larger sized L3s reduce memory contention, it's a win-win.
https://www.phoronix.com/review/amd-3d-vcache-optimizer-9950...
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